1. Field of the Invention
This invention relates to analog circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks. More particularly, this invention relates to compensation circuits incorporated with analog circuits to offset deviation in operation of the analog circuit due to variations in temperature and process.
2. Description of Related Art
Analog function circuits such as multipliers, adaptive filters, function generators, modulators, and neural networks, as is known in the art, produce a voltage output, which is proportional to an arithmetic function of two voltage inputs. As semiconductor processing has improved, more and varied circuits are formed on a semiconductor substrate. This has mandated the creation of libraries of analog function circuits or analog function cores. FIG. 1 shows a system diagram of an analog function core. There are two differential voltage inputs xcexdx, xcexdy, and one differential voltage output xcexdout. A load resistor RL is connected between the inverted and non-inverted output the differential voltage output xcexdout. The differential output voltage xcexdout is developed across a load resistor, RL and is determined by the formula:
xcexdout=kF(xcexdxxcexdy)xe2x80x83xe2x80x83EQ. 1
where:
k is a constant of proportionality or scaling
factor.
F is the arithmetic function to be performed on the two differential input signals xcexdx and xcexdy.
The load resistor RL of FIG. 1 can be formed of the two load resistors RL1 and RL2 as shown in FIG. 2. The load resistor RL1 is connected between the inverting output (xe2x88x92) of the differential output voltage xcexdout and the common mode biasing voltage source Vcm. The load resistor RL2 is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.
The voltage level present at the inverted (xe2x88x92) output terminal of the differential output xcexdout is determined as:
xcexdoutxe2x88x92=Iout1*RL1+Vcm where:
Iout1 is the output current and is determined as a function of the two differential input signals
xcexdx and xcexdy.
RL1 is the resistance value of the load resistor. Conversely, the voltage level present at the non-inverted (+) output terminal of the differential output xcexdout is determined as:
xcexdout+=Iout2*RL2+Vcm
where:
Iout2 is the output current and is determined as a function of the two differential input signals
xcexdx and xcexdy.
RL2 is the resistance value of the load resistor.
FIG. 3 shows an example of an analog function circuit implemented as a voltage multiplier with differential voltage inputs and a voltage output across a load resistor. The non-inverting input xcexdx+ of the first differential voltage input xcexdx is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M1 of a parallel connected pair of n-type MOS transistors M1 and M2. The gate of the second n-type MOS transistor M2 of the parallel connected pair of n-type MOS transistors M1 and M2 is connected to the inverting input xcexdxxe2x88x92 of the first differential voltage input xcexdx. The commonly connected sources of the parallel connected pair of n-type MOS transistors M1 and M2 are connected to a first terminal of a current source Ib3. The second terminal of the current source Ib3 is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M1 and M2 are connected to a first terminal of a current source Ib1. The second terminal of the current source Ib1 is connected to a power supply voltage source VDD. The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M1 and M2 and the first terminal of a current source Ib3 form the output terminal containing the inverted output (xe2x88x92) of the differential output voltage xcexdout.
The non-inverting input xcexdy+ of the first differential voltage input xcexdy is connected to the gate of one of the n-type metal oxide semiconductor (MOS) transistors M3 of a parallel connected pair of n-type MOS transistors M3 and M4. The gate of the second n-type MOS transistor M4 of the parallel connected pair of n-type MOS transistors M3 and M4 is connected to the inverting input xcexdyxe2x88x92 of the second differential voltage input xcexdy. The commonly connected sources of the parallel connected pair of n-type MOS transistors M3 and M4 are connected to a first terminal of a current source Ib4. The second terminal of the current source Ib4 is connected to a ground reference point. The commonly connected drains of the parallel connected pair of n-type MOS transistors M3 and M4 are connected to a first terminal of a current source Ib2. The second terminal of the current source Ib2 is connected to a power supply voltage source VDD. The junction of the commonly connected drains of the parallel connected pair of n-type MOS transistors M3 and M4 and the first terminal of a current source Ib2 form output terminal containing the non-inverted output (+) of the differential output voltage vout.
The load resistor RL1 is connected between the inverting output (xe2x88x92) of the differential output voltage xcexdout and the common mode biasing voltage source Vcm. The load resistor RL2 is connected between the non-inverting output (+) of the differential output voltage vout and the common mode biasing voltage source Vcm.
The gates of the parallel connected pair of n-type MOS transistors M1 and M2 and the gates of the parallel connected pair of n-type MOS transistors M3 and M4 are biased externally with a constant voltage source VB (not shown) to cause the parallel connected pair of n-type MOS transistors M1 and M2 and the parallel connected pair of n-type MOS transistors M3 and M4 to operate in the saturation region. This insures that any voltage developed from the drains to the sources of the parallel connected pair of n-type MOS transistors M1 and M2 or the parallel connected pair of n-type MOS transistors M3 and M4 does not effect the saturation drain-to-source current Ids through the parallel connected pair of n-type MOS transistors M1 and M2 or the parallel connected pair of n-type MOS transistors M3 and M4.
The drain-to-source saturation current Idssat of each of the parallel connected pair of n-type MOS transistors M1 and M2 or the parallel connected pair of n-type MOS transistors M3 and M4 is found by the formula:
Idssat=K(VGSxe2x88x92VT)2
where:
VGS is the gate-to-source of each MOS transistor.
VT is the threshold voltage at which MOS transistor begins to conduct or turn-on.
K is a process constant found as the function   K  =                    μ        s            ⁢              (                              C            ox                    2                )              ⁢          (              W        L            )      
xe2x80x83where:
xcexcs is the mobility of the bulk doped semiconductor material that forms the channel.
Cox is the capacitance of the gate oxide of the MOS transistors.   (      W    L    )
is the width-to-length ratio of the MOS transistors.
As can be shown from Einstein""s Relationship, the mobility xcexcs of the semiconductor material is dependent upon the absolute temperature of operation. Further, any changes in the process that effects the doping of the semiconductor material will further change the value of the mobility xcexcs of the semiconductor material. Additionally, process changes may effect the geometric values of the width-to-length ratio       (          W      L        )    ,
as well as the thickness of the insulating material that forms the gate oxide, which will change the values of the capacitance Cox.
It can be shown that the output currents Iout1 and Iout2 can be calculated by the formula:       I    out1    =            I      out2        =                            μ          n                ⁢                  (                      C            ox                    )                    ⁢              (                  W          L                )            *              v        x            *              v        y            
where:
xcexcn is the mobility of the bulk doped semiconductor material that forms the channel.
Cox is the capacitance of the gate oxide of the parallel connected pair of n-type MOS transistors M1 and M2 and the parallel connected pair of n-type MOS transistors M3 and M4.   (      W    L    )
is the width-to-length ratio of the parallel connected pair of n-type MOS transistors M1 and M2 and the parallel connected pair of n-type MOS transistors M3 and M4.
Thus, the voltage level present at the inverted (xe2x88x92) output terminal of the differential output xcexdout is determined as:                               Vout          +=                                    I              out1                        *            RL1                          =                              μ            n                    ⁢                                    C              ox                        ⁡                          (                              W                L                            )                                *                      v            x                    *                      v            y                    *          RL1                                    Eq        .                  xe2x80x83                ⁢        3            
and the voltage level present at the non-inverted (+) output terminal of the differential output xcexdout is determined as:                               Vout          -=                                    I              out2                        *            RL2                          =                              μ            n                    ⁢                                    C              ox                        ⁡                          (                              W                L                            )                                *                      v            x                    *                      v            y                    *                      RL2            .                                              Eq        .                  xe2x80x83                ⁢        4            
An object of this invention is to provide an analog integrated circuit such as a multiplier, adaptive filter, function generator, modulator, or neural network whose output voltage signal is independent from variations in temperature and process.
Another object of this invention is to provide a compensation circuit in connection with or integrated with an analog circuit such as a multiplier, adaptive filter, function generator, modulator, or neural network to make the output signal of the analog circuit not vary with changes in temperature and manufacturing process.
To accomplish these and other objects a temperature and process independent analog integrated circuit has an analog integrated function core circuit. The function core circuit has a first differential pair of input terminals to receive a first input signal, a second differential pair of input terminals to receive a second input signal, and a differential pair of output terminals. The differential pair of output terminals contains an output signal that is a function of a scaling constant, the first input signal, and the second input signal.
The analog integrated circuit has a first and a second loading device. The first loading device has a first terminal connected to an inverted terminal of the differential pair of output terminals, a second terminal connected to a common mode voltage terminal, and a third terminal. A loading control voltage at the third terminal controls a loading on a voltage signal present at the inverted terminal by the first loading device. The second loading device has a first terminal connected to an non-inverted terminal of the differential pair of output terminals, a second terminal connected to the common mode voltage terminal, and a third terminal. The loading control voltage also at the third terminal controls the loading on a voltage signal present at the non-inverted terminal by the second loading device. The first and second loading devices in the preferred embodiment are MOS transistors of a second conductivity type and are biased by a loading device controller to operate in a linear operation region of the first and second loading devices.
The loading device controller within the analog integrated circuit compensates for changes in voltage level of the output signal due to variations in temperature and variations in manufacturing process within the function core circuit. The loading device controller has a loading control voltage terminal to provide the loading control voltage. The loading device controller has a first MOS transistor of a first conductivity type with a gate connected to a first control bias voltage source, a source connected to the ground reference point, and a drain. The loading device controller has a second MOS transistor of the first conductivity type with a source connected to the drain of the first MOS transistor of the first conductivity type, a gate, and a drain. A first MOS transistor of the second conductivity type has a source connected to the common mode voltage terminal, a drain connected to the second MOS transistor of the first conductivity type, and gate connected to the loading control voltage terminal. A first differential amplifier has an inverting input connected to a second control bias voltage source, a non-inverting input connected to the connection of the drain of the first MOS transistor of the second conductivity type and the drain of the second MOS transistor of the first conductivity type, and an output connected to the gate of the first MOS transistor of the second conductivity type and forms the loading control voltage terminal. The voltage present at the connection of the drain of the first MOS transistor of the second conductivity type and the drain of the second MOS transistor of the first conductivity type is maintained at a voltage level equal to a voltage level of the second bias control voltage source. A second differential amplifier has an inverting input connected to the connection of the drain of the first MOS transistor of the first conductivity type and the source of the second MOS transistor of the first conductivity type, a non-inverting input connected to a third biasing control voltage source, and an output connected to the gate of the second MOS transistor of the first conductivity type. The voltage at the connection of the drain of the first MOS transistor of the first conductivity type and the source of the second MOS transistor of the first conductivity type is maintained at the voltage level of the third biasing voltage source.
Further, the analog integrated core circuit has a biasing circuit. The biasing circuit has the common mode voltage terminal to provide a common mode voltage to the first and second loading devices and in communication with the compensation circuit provide the first, second and third control bias voltage sources.
The bias circuit includes a bandgap referenced current source. The bandgap referenced current source provides a reference current that is independent of temperature. A current mirror has a reference terminal that is responsive to the reference current source, a first terminal coupled to the compensation circuit to provide a first current proportional to the reference current and second terminal to provide a second current proportional to the reference current.
The bias circuit has a first resistor connected to the first terminal of the current mirror. A threshold voltage generator is connected between a second terminal of the first resistor and a ground reference point such that the first bias voltage source is provided to the first to the compensation circuit.
A voltage divider is connected between the second terminal of the current mirror and the ground reference point. The voltage divider has a first terminal to provide the second bias voltage source to the compensation circuit and a second terminal to provide a third bias voltage source to the compensation circuit. A voltage buffer has an input terminal that is in communication with the connection of the second terminal of the current mirror and the voltage divider. An output terminal is connected to the common mode voltage terminal to provide the common mode voltage source in response to a fourth biasing voltage present at the connection of the second terminal of the current mirror and the voltage divider.
If the analog integrated core circuit is a multiplier circuit, it has a first and a second parallel connected pair of MOS transistors of a first conductivity type. A gate of one MOS transistor of the first parallel connected pair of MOS transistors is connected to an inverting input of the first differential pair of input terminals. A gate of the other MOS transistor of the parallel connected MOS transistors is connected to a non-inverting input of the first differential pair of input terminals. Commonly connected drains are connected to the inverted terminal of the differential pair of output terminals. Likewise, gate of one MOS transistor of the second parallel connected pair of MOS transistors is connected to an inverting input of the second differential pair of input terminals. A gate of the other MOS transistor of the parallel connected MOS transistors is connected to a non-inverting input of the second differential pair of input terminals. Commonly connected drains are connected to the non-inverted terminal of the differential pair of output terminals. A first biasing constant current source is connected between a power supply voltage source and the commonly connected drains of the first parallel connected MOS transistors, and a second biasing constant current source is connected between commonly connected sources of the first parallel connected MOS transistors and a ground reference point. A third biasing constant current source is connected between a power supply voltage source and the commonly connected drains of the second parallel connected MOS transistors, and a fourth biasing constant current source is connected between commonly connected sources of the second parallel connected MOS transistors and a ground reference point.